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Yield tool minimizes design re-spin

Posted: 20 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:management tool yield? re spin? design test?

At the IEEE International Symposium on Quality Electronic Design (ISQED) conference, Synopsys Inc. introduced Yield Explorer, a new yield management tool that expedites the discovery and mitigation of yield limiters in leading-edge ICs.

Yield Explorer minimizes design re-spin through rapid and comprehensive capture of design-process-test interactions causing low yield, according to the company.

Today, users using traditional yield management methods devise lengthy, manual workarounds to move data between yield management and EDA tools.

"Yield Explorer enabled us to achieve a tenfold improvement in time to results when investigating the causes of test failures using our volume diagnostics approach," said Davide Appello, DfX technologies senior expert at STMicroelectronics. "With Yield Explorer, we were able to rapidly isolate, prioritize and correct the significant design issues within the first batch of product chips."

Yield Explorer's GUI is structured around a layout viewer for superposition of test failures on the corresponding layers of physical design.

In addition to the wide range of analytical functions, users also benefit from the industry standard Tcl scripting environment built into the GUI.

This environment can accommodate very large volumes of data with customer-specific data naming and content requirements. Its dynamically extendable data model provides a way of assimilating new types and formats of data without any loss of information or efficiency.

"Our customers have stressed the need for bringing design information into yield analysis," said Howard Ko, senior VP and general manager of the silicon engineering group at Synopsys. "Yield Explorer is the only yield management tool that links all aspects of the design, manufacturing and test flows into a single data-bank."

- Nicolas Mokhoff
EDA DesignLine

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