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110nm CMOS squeezes extra die per wafer

Posted: 27 Mar 2009 ?? ?Print Version ?Bookmark and Share

Keywords:110nm CMOS? process technology? logic wafer?

Foundry provider Silterra Malaysia Sdn. Bhd. has debuted a foundry-compatible copper-based 110nm CMOS logic process technology.

The technology, codenamed CL110G, offers a 10 percent optical shrink for the copper-based 130nm CMOS logic process Silterra has had in production for more than two years. The electrical device specification and Spice model of CL110G are optimized to match with a customer's original 130nm design, according to Silterra.

Customers can use the new technology to squeeze extra die per wafer, said Yit Loong Lai, Silterra's VP of worldwide sales and marketing. The technology is now ready for customer prototypes.

"In the current economy downturn, consumers are more cost conscious, but their appetite for high performance and low power handheld gadgets remains high," Lai said in a statement.

Silterra said CL110G technology is optimized for high-performance and high-density complex designs. The technology features eight layers of dual damascene copper metallization, borderless contacts and vias with FSG inter-metal dielectric.

CL110G is supported by a complete set of foundry foundation IP from Virage Logic, ARM and other IP vendors, the company said. The design flow is also validated in Synopsys Inc. and Mentor Graphics Corp. platforms.

- Dylan McGrath
EE Times

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