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Joint effort aims to enable 3D semiconductors

Posted: 01 Apr 2009 ?? ?Print Version ?Bookmark and Share

Keywords:TSV joint effort? semiconductors 3D? thinning wafer?

Applied Materials Inc. and Disco Corp. have announced a joint effort to develop wafer thinning processes for fabricating through-silicon vias (TSVs) in 3D semiconductors. The two companies will be working together to develop integrated, high-performance process flows intended to lower the cost, reduce the risk and accelerate time-to-market for customers' next-generation chips.

TSV technology is a new method that enables higher density, lower-power devices in a smaller footprint by vertically stacking chips. To make this 3D stack, each chip or wafer layer must be reduced in thickness by up to 90 percent and bonded to a temporary carrier to maintain structural integrity during the thermal and mechanical stresses of semiconductor processing.

Combining Disco's precision grinding equipment with Applied's etch, dielectric deposition, physical vapor deposition and chemical mechanical planarization systems, the two companies expect to develop wafer thinning and post-thinning processes of wafers bonded to silicon and glass carriers. Some of the key technical requirements in developing manufacturing-worthy equipment and process solutions are wafer structural and edge integrity, handling, dimensional control, particle control, stress management, and thermal profile control.

"The alliance of Applied's process integration expertise and our leading wafer thinning systems is great news for chipmakers planning to use TSV technology," said Nobukazu Dejima, president of Disco Hi-Tec America Inc.

"We're pleased to work with Disco to advance this exciting and disruptive technology," said Hans Stork, group VP and chief technology officer of Applied's silicon systems group.

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