QDR II SRAM interface for Virtex-5 devices

This application note describes the implementation and timing details of a Quad Data Rate (QDR II) SRAM interface for Virtex-5 devices. The synthesizable reference design leverages the unique I/O and clocking capabilities of the Virtex-5 family to achieve performance levels of 300MHz (600 Mbits), resulting in an aggregate throughput for each 36bit memory interface of 43.2Gbit/s.

The design greatly simplifies the task of read data capture within the FPGA while minimizing the number of resources used. A straightforward user interface is provided to allow simple integration into a complete FPGA design utilizing one or more QDR II interfaces.

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