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Unlock Micron's 50nm DRAM technology

Posted: 09 Apr 2009 ?? ?Print Version ?Bookmark and Share

Keywords:DRAM? Micron 50nm technology? SDRAM?

After analyzing state-of-the-art DRAM devices from the Korean manufacturers Samsung and Hynix Semiconductors, Semiconductor Insights gave Micron Technology Inc. its turn under the magnifying glass. With the help of advanced imaging techniques, SI analyzed the process technology used to fabricate Micron's newest 1Gbit DDR2 50nm SDRAM and is now ready to reveal some of the design trends introduced by the North American DRAM manufacturer.

The latest DRAM offering from Micron can be technically defined as a true 50nm product. This was confirmed by the accurate measurement of the device's wordline half-pitch. By comparison, the half-pitch dimensions of the Samsung and Hynix devices are respectively 58nm and 54nm. It is now established that the patterning of 50nm-size features is pushing the limits of standard 193nm "dry" photolithography, even with the use of resolution-enhancement techniques. To produce these densely packed structures, an advanced lithography approach is required, such as immersion lithography or double patterning. Interestingly, Micron appears to be using advanced lithography techniques not only for the wordline definition but at other critical layers as well. For example, the minimum metal 2 line pitch observed on the Micron chip is 150nm. This critical dimension is on par with what is seen nowadays in advanced logic processes such Intel's 45nm technology. The move to immersion lithography at multiple layers would represent a formidable capital investment for Micron, and it is more likely that an immersion-light approach is adopted at this time. Micron is keeping quiet about whether or not they are using immersion lithography in production.

'Smallest' cell size
Micron's 50nm wordline half-pitch results in the smallest cell size ever seen in a DRAM device. Micron first introduced its 6-F? cell design at the 0.11?�m technology node (analyzed by SI back in 2004), and this same proven layout is still in use at the 50nm node. The 6-F? cell from Micron is rectangular and measures 3-F in the bitline direction and 2-F in the wordline direction, where F is the half-pitch of the respective lines. In this design, an isolation line, or dummy wordline, is used to isolate two adjacent cells. The remarkable aspect of this design is that by removing the dummy wordline and tilting the active areas by 45, a 4-F? layout could be obtained. It remains to be seen if a sufficient capacitor could fit in such a small cell or if the active regions could be properly isolated from each other. However, Micron's current cell design has the potential to become the first to be converted to the smaller 4-F? size.

It must be noted that Micron's cell size does not exactly correspond to the nominal 6-F?; size where F = 50nm. This is because the bitline pitch is slightly relaxed. Hynix achieves a smaller 54nm bitline half-pitch in their device; however, the use of a conventional 8-F? cell layout results in a cell size that is effectively 33 percent larger. Overall, Micron's 1Gbit DDR2 die size is 8 percent smaller than Samsung's corresponding device and 11 percent smaller than the Hynix die. In theory, Micron could achieve an even larger die-size difference, but Micron's die efficiency (i.e., the size of the memory cell array versus the total die size) was calculated to be slightly lower than the two Korean devices.

In a modern stacked-capacitor DRAM device, the structure of the storage capacitor can be thought of as a vertical tube made of titanium nitride (TiN) with an aspect ratio of about 10:1. To maximize the capacitance value of the cell in high-performance DRAM devices, it is important to form the capacitor dielectric and top electrode, or cell plate, on both inner and outer surfaces of the tube. To achieve this double coverage, the dielectric material surrounding the storage nodes needs to be removed during the fabrication process. This step normally results in an array of densely populated, fragile tubular structures that have no lateral support.

To improve the mechanical stability of the storage capacitors, Micron is using a thick nitride spacer layer at the top of the storage nodes. It's easy to visualize such a structure. Just think of those handy plastic rings used to hold a six pack of aluminum cans of your favorite beverage. In this analogy, the aluminum cans would be the storage nodes and the plastic rings are the nitride spacer that keeps the nodes apart from each other. This idea is neither new nor exclusive to Micron since Samsung does something similar. However, Micron's implementation is slightly more elegant and efficient in that it removes the dielectric material only in the memory cell array and leaves it intact in the periphery. This is achieved by properly isolating the array area from the periphery and by creating openings in the spacer layer so that the dielectric material present underneath can be removed. The use of this storage-node spacer adds to the overall complexity of an already complicated DRAM process, but the improved stability and yield no doubt compensate for the added cost.

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