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Unlock Micron's 50nm DRAM technology

Posted: 09 Apr 2009 ?? ?Print Version ?Bookmark and Share

Keywords:DRAM? Micron 50nm technology? SDRAM?

Switch to zirconium oxide
A major change to Micron's process flow at 50nm was to switch from hafnium oxide as the main component of the capacitor dielectric to zirconium oxide. Zirconium oxide has a higher dielectric constant and lower leakage than hafnium oxide and now represents the de facto standard for advanced DRAM devices. This change from Micron highlights the need for DRAM manufacturers to extract the maximum capacitance from the current storage-node design without having to make significant changes to the physical size and shape of the capacitors.

Micron has been using copper metallization for the upper interconnects for many product generations. For the first time at the 50nm node, a second manufacturer (Elpida) has announced the integration of copper in a DRAM device. However, one process feature that still distinguishes Micron from the rest of the DRAM crowd is the use of raised source and drain (S/D) regions formed by selective epitaxy. The elevation of these regions above the substrate allows shallower S/D profiles within the substrate, which, in turn, improves the performance of short-channel MOS transistors. The raised S/D regions probably also benefit the recessed channel array transistors (RCAT), which are now widely adopted by DRAM manufacturers to help reduce leakage by effectively increasing the size of the transistor channel in the tightly spaced memory array. By having the S/D partially moved above the substrate, Micron can achieve the same leakage-reduction effect with a shallower RCAT trench structure. In fact, the RCAT trenches in the Micron device are only half as deep as the ones used by Samsung.

With their latest 50nm process technology, Micron seems to have struck the right balance between investment in new technologies (advanced lithography techniques, improved high-k materials) and conservative design decisions (proven 6-F? layout, no scaling down of gate dielectrics). Their balanced approach positions Micron well to keep up with the ITRS roadmap for the technology nodes to come. At the same time, it will help them control production costs while gradually improving yield and reducing cycle time, which are of the utmost importance in the fabrication of DRAM products.

- Carl Wintgens
Senior Process Analyst, Semiconductor Insights

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