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High-performance DDR2 SDRAM interface in Virtex-5 devices

Posted: 13 Apr 2009 ?? ?Print Version ?Bookmark and Share

Keywords:SDRAM? FPGA? interface? application note?

DDR2 SDRAM uses a source synchronous interface for transmission and reception of data. On a read, the data and strobe are transmitted edge aligned by the memory. To capture this transmitted data using Virtex-5 FPGAs, either the strobe and/or data can be delayed. In this design, the read data is captured in the delayed strobe domain and recaptured in the FPGA clock domain using a combination of the Input Double Data Rate and Configurable Logic Block flip-flops.

This application note describes a 667Mbit/s DDR2 SDRAM interface implemented in a Virtex-5 device. A customized version of this reference design can be generated using the Xilinx Memory Interface Generator tool.

View the PDF document for more information.

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