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OTP memory IP tailored for 65nm designs

Posted: 27 Apr 2009 ?? ?Print Version ?Bookmark and Share

Keywords:memory IP? memory OTP? 65nm design?

Sidense has released its 1T-OTP one-time programmable (OTP) memory IP for customer designs at the 65nm process node. Sidense claims to be the first embedded OTP vendor to announce high density (above 1Mbit) product availability for both standard-logic and low-power 65nm implementation.

The OTP memory was selected for use in ParkerVision's 65nm d2p mobile handset solution, leveraging the small size, low power and speed of programming of the solution.

The 1T-OTP offers low power, a small footprint and high security technology for embedded non-volatile memory arrays. The silicon-proven, 'foundry friendly' OTP lets designers choose from a wide range of foundries and processes for implementing their devices.

Sidense SiPROM NVM arrays, based on the company's patented 1T-Fuse technology, have been silicon proven in 65nm for both standard-logic and low-power processes and are available in densities up to 8Mbit. Memory arrays are available from 180nm down to 55nm at many popular foundries

- Gregory Quirk
Mobile Handset DesignLine





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