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14bit ADC cuts digital feedback

Posted: 29 Apr 2009 ?? ?Print Version ?Bookmark and Share

Keywords:ADC? digital feedback? analog digital converter?

From Linear Technology Corp. comes a low-power 14bit, 150MSps ADC that dissipates only 149mW, less than one-third the power of competitive solutions. This new benchmark enables portable applications limited by stringent power budgets to extend their performance capabilities, as well as providing higher operating efficiency and reduced recurring operating costs for 3G/4G LTE and WiMAX base station equipment.

In addition to offering considerably lower power, the LTC2262 integrates two unique features for reducing digital feedback in situations where even good layout practice may fail. These features in combination with low power ease the task of designing with high speed ADCs in a wide variety of applications, including portable medical imaging and ultrasound, portable test and instrumentation, non-destructive test equipment, software defined radios and cellular base stations.

Digital feedback occurs when energy from ADC outputs couples back into the analog section, causing interaction that appears as odd shaping in the noise floor and spurs in the ADC output spectrum. The worst situation is at midscale, where all outputs are changing from ones to zeroes, or vice versa, generating large ground currents that couple back into the input. To combat this effect, the LTC2262's proprietary alternate bit polarity mode inverts all of the odd bits before the output buffers to equalize the number of ones and zeroes switching. This method effectively cancels the large ground plane currents that contribute to digital feedback. In addition to the alternate bit polarity mode, an optional data output randomizer is also available for reducing interference from the digital outputs. The randomizer decorrelates the digital output to reduce the likelihood of repetitive code patterns that couple back into the ADC input, causing unwanted tones in the output spectrum. Both digital feedback reduction techniques have proven to improve spurious free dynamic range (SFDR) performance by 10dB to 5dB.

Operating from a low 1.8V analog supply, the LTC2262 achieves significant power savings without sacrificing AC performance. This ADC offers SNR performance of 72.8dB and spurious free dynamic range (SFDR) of 88dB at baseband. Ultralow jitter of 0.17psRMS allows undersampling of IF frequencies with excellent noise performance.

In addition, the LTC2262's digital outputs can be set to full rate CMOS, double data rate CMOS or double data rate LVDS. Double data rate digital outputs allow data to be transmitted on both the rising edge and the falling edge of the clock, reducing the number of data lines needed by half. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.

Offered in a 6mm x 6mm QFN package, the LTC2262 includes a clock duty cycle stabilizer circuit to facilitate non-50 percent clock duty cycles, programmable digital output timing, programmable LVDS output current and optional LVDS output termination. These features combine to make the data transmission between the ADC and the digital receiver more flexible.

The LTC2262 joins a family of pin-compatible 14- and 12bit ADCs, with sampling rates ranging from 25MSps to 150MSps, and power dissipation of 35mW to 149mW, respectively. Demonstration boards and samples are available online at www.linear.com. The LTC2262 is offered in commercial and industrial temperature grades, and is priced at $57 each for the 14bit LTC2262-14, and $35 each for the 12bit LTC2262-12 in 1,000-piece quantities.

All parts are available in optional lead-free packages for RoHS compliance.





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