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LatticeECP3 Serdes/PCS usage guide

Posted: 12 May 2009 ?? ?Print Version ?Bookmark and Share

Keywords:LatticeECP3 usage guide? Serdes? FPGA?

The LatticeECP3 FPGA family combines FPGA fabric, I/Os and up to 16 channels of embedded Serdes with associated Physical Coding Sublayer (PCS) logic. The PCS logic can be configured to support numerous industry-standard, high-speed serial data transfer protocols.

Each channel of PCS logic contains dedicated transmit and receive Serdes for high-speed, full-duplex serial data transfer at data rates up to 3.2Gbit/s. The PCS logic in each channel can be configured to support an array of popular data protocols including GbE, XAUI, PCI Express, SRIO, CPRI, OBSAI, SD-SDI, HD-SDI and 3G-SDI. In addition, the protocol-based logic can be fully or partially bypassed in a number of configurations to allow users flexibility in designing their own high-speed data interface.

The PCS also provides bypass modes that allow a direct 8bit or 10bit interface from the Serdes to the FPGA logic. Each Serdes pin can also be independently DC coupled and can allow for both high-speed and low-speed operation on the same Serdes pin for applications such as Serial Digital Video.

View the PDF document for more information.

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