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LatticeECP3 sysCLOCK PLL/DLL design and usage guide

Posted: 13 May 2009 ?? ?Print Version ?Bookmark and Share

Keywords:PLL? LatticeECP3? architecture device?

This application note describes the clock resources available in the LatticeECP3 device architecture. Details are provided for primary clocks, secondary clocks and edge clocks as well as clock elements such as PLLs, DLLs, clock dividers and more.

LatticeECP3 devices provide global clock distribution in the form of eight quadrant-based primary clocks and flexible secondary clocks. Two edge clocks are also provided on the left, right and top edges of the device. Other clock sources include clock input pins, general logic, PLLs, DLLs, DCSs and clock dividers.

View the PDF document for more information.





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