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USB 3.0 transceiver IC ensures data integrity

Posted: 15 May 2009 ?? ?Print Version ?Bookmark and Share

Keywords:transceiver chip? USB 3.0? integrity data?

Texas Instruments Inc. will demonstrate at next week's USB Developers Conference in Tokyo, Japan a 5Gbit/s transceiver test chip that it says will speed the implementation of the emerging SuperSpeed USB 3.0 specification.

The test chip, designed to the USB 3.0 specification ver. 1.0, was designed to drive and receive signals over 4m USB 3.0 cables to ensure data integrity.

The SuperSpeed USB interface, released last November, runs at up to 5Gbits/s and can deliver as much as 300MBps of data at the application layer.

TI said the device has already been tested with Synopsys' intellectual property (IP) digital controller at the USB-IF SuperSpeed Peripheral Interoperability Lab.

"Demonstrating interoperability between Synopsys' DesignWare SuperSpeed USB digital controller and TI's USB transceiver gives designers confidence that the IP functions successfully in a real-world system environment," said John Koeter, VP of marketing for the solutions group at Synopsys.

Synopsys said in November when the USB 3.0 spec was released that it would have PHY, controller and verification IP for USB 3.0 available early this year for select partners. It said the IP would be generally available in 2H 09.

The USB Implementers Forum that developed the spec announced in early March it has set up an interoperability lab to test devices initially using a prototype software stack and test tools. The group aims to evolve the tools based on user feedback until they are ready to become part of a final certification program.

The first in TI's SuperSpeed USB family of devices, the TUSB1310 transceiver, will sample in Q4 09, with volume production expected in Q1 10. Evaluation modules will also be available to interface the TUSB1310 to a variety of processor and FPGA implementations.

The transceiver has an integrated spread spectrum PLL to support multiple input reference frequencies, including 20MHz, 25MHz, 30MHz and 40MHz as well as PIPE3 and ULPI compliant interfaces.

TI says the transceiver will save system cost by eliminating the need for an external spread spectrum clocking device. There will be interoperability across a wide selection of ASIC/FPGA platforms so that designers can work with the same USB device, regardless of the processor platform.

- John Walko
EE Times Europe





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