Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > FPGAs/PLDs

LatticeECP3 memory usage guide

Posted: 20 May 2009 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? RAM? memory?

This technical application note discusses memory usage for the LatticeECP3 family of FPGA devices. It is intended to be used by design engineers as a guide to integrating the Embedded Block RAM (EBR)- and PFU-based memories for this device family in ispLEVER.

The LatticeECP3 architecture provides many resources for memory-intensive applications. The sysMEM EBR compliments its distributed PFU-based memory. Single-Port RAM, Dual-Port RAM, Pseudo Dual-Port RAM and ROM memories can be constructed using the EBR. The LUTs and PFUs can implement Distributed Single-Port RAM, Dual-Port RAM and ROM. The internal logic of the device can be used to configure the memory elements as FIFO and other storage types.

View the PDF document for more information.

Article Comments - LatticeECP3 memory usage guide
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top