MEMS/IC environment handles co-simulation, co-verification

Traditionally, MEMS chip design requires a separate design effort for a CMOS ASIC, whether the two are destined for separate chips or are to be housed on the same die. The MEMS structures are designed using a 3D computer-aided design (CAD) system, and tedious hand translation of process parameters is required when transferring the MEMS design to a semiconductor circuit simulator and verification tool.

Coventor worked with Cadence to preset its new MEMS+ 3D CAD offering to dovetail with Cadence's Virtuoso Schematic Editor, allowing automatic translation of all necessary dimensions and process parameters from MEMS+ to Virtuoso. MEMS+IC thus unites the two design efforts, enabling full co-simulation and co-verification.

"MEMS designers have a 3D environment for creating their MEMS models; then they export all the views and files needed [for] layout in Cadence Virtuoso Schematic Editor," said Joost van Kuijk, VP of marketing and business development at Coventor. "The models are heavily parameterized, so you can actually do all of the things you need to do over on the Cadence side."

MEMS+IC allows bidirectional transfer of 3D behavioral models for the MEMS mechanical device between the Coventor 3D CAD and Virtuoso EDA environments. "We are now able to take the MEMS model and perform simulation and verification across our simulation technologies," said John Pierce, director of marketing for analog simulation at Cadence.

Automatically transferring parameters into the EDA tool from the 3D CAD environment not only saves time but also permits all manufacturing- and design-dependent variables to be tweaked after simulation, then transferred back to the 3D CAD environment for visualization and for making changes to the MEMS device should they be required, the companies said.

- R. Colin Johnson
EE Times