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Rambus details DDR4 DRAM roadmap

Posted: 28 May 2009 ?? ?Print Version ?Bookmark and Share

Keywords:DDR4? DRAM? interconnect? NAND flash?

Rambus Inc. has unveiled a set of new and existing interconnect technologies it claimed will meet the needs of main memory in 2011 and beyond. It hopes the industry adopts the techniques as part of a pending DDR4 DRAM standard.

The concepts are promising, but a history of intellectual property disputes clouds the road to adopting them. Rambus is in litigation with three of the four top DRAM makers, one of the cases stretching into its ninth year.

Some of the IP issues originated in work on memory interconnects in the JEDEC group that defines next-generation DRAM standards, a group in which Rambus no longer participates. JEDEC executivesand a handful of the group's membersdeclined to comment on the status or outlook for DDR4 for this story.

As part of its announcement, Rambus outlined a handful of market requirements it believes will be key for main systems memory interconnects in 2011 and beyond. They include doubling today's DDR3 per-pin data rates to 3,200Mbit/s, slashing active and idle power rates significantly and maintaining support for multiple DIMMs per memory channel.

The company disclosed two new technologies as part of a new main memory initiative to address those requirements, module threading and a new single-ended version of its near-ground signaling technology.

As the name suggests module threading splits a link into two parallel threads. It aims to tap the significant unused bandwidth of a DDR3 link while cutting in half the power used to activate a row.

The two threads are generated by accessing a module on both the right and left side in an out-of-phase fashion and pipelining the data. Rambus has shown power reductions of 20 percent using module threading on a prototype DDR3 DIMM.

The other new techniquenear ground signalingwas applied in a differential version in an ISSCC paper in February 2007. The new version uses single-ended signaling. It opens the door to use of power sources as low as 0.5V and 80 percent reductions in signaling I/O thanks to very low voltage swings.

As part of its main memory initiative, the company is packaging three of its existing technologies along with the two new ones. FlexPhase enables high data rates by overcoming the speed limitations of the direct strobing technology used in DDR3, Dynamic Point-to-Point technology is a signaling technique aimed to boost capacity and FlexClocking reduces clocking power by eliminating the need for a phase-locked loop on the DRAM.

The first two techniques are part of the Rambus XDR memory architecture. The latter technique was introduces as part of the company's mobile memory initiative announced in February.

Rambus claims that used in concert the five techniques can provide twice the bandwidth of a DDR3 link at nearly half the active power and a fraction of the idle power while still supporting multiple DIMMs per memory channel. The company has released a white paper available online detailing the techniques.


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