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SEU strategies for Virtex-5 devices

Posted: 05 Jun 2009 ?? ?Print Version ?Bookmark and Share

Keywords:Virtex-5? SEU strategy? single event upset?

Xilinx devices are designed to have an inherently low susceptibility to single event upsets (SEUs). This application note provides a substantial discussion of strategies and representative calculations for handling SEUs with an emphasis on reliability when addressing these low probability events.

This application note is accompanied by a reference design for use with the Virtex-5 FPGA ML505 evaluation platform (but can port to other hardware) and an SEU controller macro, which can be included in any Virtex-5 FPGA design to implement an SEU detection and correction scheme. These supplements can be used to evaluate the different methods of dealing with SEUs.

Due to the infrequent and unpredictable nature of real SEUs, small scale testing of their effects and system verification is impractical. For this reason, the SEU controller macro and reference design can emulate an SEU by deliberately injecting an error into the FPGA configuration so that its subsequent detection and correction can be confirmed. Injection of errors can also be used to assess SEU mitigation circuits implemented in a design. This application note focuses on the Virtex-5 family although much is applicable to the Extended Spartan-3A family.

View the PDF document for more information.

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