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On-chip memory usage guide for LatticeSC devices

Posted: 10 Jun 2009 ?? ?Print Version ?Bookmark and Share

Keywords:LatticeSC architecture? memory? block embedded?

This application note discusses memory usage in the LatticeSC family of devices. It is intended for design engineers as a guide to designing and integrating the EBR-based and PFU-based memories of the LatticeSC device family using Lattice ispLEVER design software.

The LatticeSC architecture provides many resources for memory-intensive applications. The sysMEM Embedded Block RAM (EBR) complements its distributed PFU-based memory. Single-port RAM, dual-port RAM, pseudo dual-port RAM, FIFO and ROM memories can be constructed using the EBR. LUTs and PFU can implement distributed single-port RAM, dual-port RAM and ROM. The internal logic of the device can be used to configure the memory elements as FIFO and other storage types.

The EBR block RAM and PFU RAM are referred to as memory primitives and their capabilities are described later in this application note. The memory primitives can be used in two ways:

? Using IPexpressThe IPexpress GUI allows users to specify the memory type and size required. IPexpress takes this specification and constructs a netlist to implement the desired memory by using one or more of the memory primitives.

? Using the PMI (parameterizable module inferencing)PMI allows experienced users to skip the graphical interface and use the configurable memory modules on the fly from the ispLEVER Project Navigator. The parameters and control signals can be set in either Verilog or VHDL. The top-level design includes the defined parameters and signals so the interface can automatically generate the black box during synthesis.

The remainder of this document discusses these approaches as well as memory modules and memory primitives.

View the PDF document for more information.

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