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Low-power options for Async/Page CellularRAM

Posted: 10 Jun 2009 ?? ?Print Version ?Bookmark and Share

Keywords:CellularRAM? low power operation? register configuration?

Micron CellularRAM devices are designed to be backward compatible with 6T SRAM, early-generation asynchronous, and page PSRAM. This backward compatibility is essential for designs requiring high-speed and low-power operation. CellularRAM memory also provides a burst NOR flash-compatible interface that allows designers to take their designs to the next performance level.

CellularRAM device features include: support for 16Mbit through 128Mbit densities; small-package footprint FBGA devices; known good devices (KGD); burst NOR flash compatible interface; asynchronous, page and high-speed (up to 104MHz) burst interface; low-power options, including partial array refresh (PAR), low standby current and deep power-down (DPD) mode; and hidden refresh control.

This application note describes the low-power operational modes available on the asynchronous/page CellularRAM devices and the use of the ZZ# input in conjunction with the configuration register (CR) settings to control these modes.

View the PDF document for more information.





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