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PCIe 3.0 cores support up to 16 lanes

Posted: 10 Jun 2009 ?? ?Print Version ?Bookmark and Share

Keywords:PCIe 3.0? PCIe cores? controller?

Gennum Corp.'s Snowbush IP group has completed silicon core designs of a controller and PHY device for PCIe version 3.0. The company also signed up PLX Technology, a PCI bridge and switch chipmaker, as its first customer.

The next generation of the board-level interconnect has a maximum theoretical throughput of 8GT/s. The PCI Special Interest Group (PCI SIG) doesn't expect adoption of the technology in multiple markets until 2012 and the standard itself is said to be in a version 0.7.

Nevertheless, the DesignWare group at Synopsys, a main competitor for Gennum, says it also expects customers to take delivery of its PHY and controller cores before the end of the year. "Our IP is based on the most recent (0.7) version of the PCIe 3.0 specification and of course will be updated when the final version is released," said Navraj Nandra, director of analog/mixed-signal IP for Synopsys.

The cores are based on a multistandard Serdes Gennum taped out in a 65nm process in 2007. Gennum ported that design to a 40nm TSMC process and added a five-tap decision feedback equalization (DFE) block to ensure signal integrity at the high data rates of PCIe 3.0.

The Gennum cores support up to 16 lanes of Express at the 2.5-, 5- and 8GT/s data rates specified by the three generations of the standard. With the addition of more gates, the cores can support different speeds simultaneously on different lanes.

The cores use a cut-through switching technique to keep latency low. They support all required PCIe 3.0 features, including the new capability for atomic transactions that can ease data sharing for some operations with multicore processors. They use a 0.9V power supply, and can be fabricated in a 65 nm process if a higher power supply is used.

PLX executives said they chose the Gennum cores for technical and time-to-market reasons.

"PCIe Gen 3 signaling poses unique challenges that require a high degree of programmability in the Serdes to address the wide spectrum of usages," said Vijay Meduri, VP of engineering for PLX's switching group. "Snowbush provides a compelling solution with the required DFE and transmit-emphasis schemes that will enable our customers to make the transition to Gen 3," he added.

The immanent delivery of the GDS files "enables [PLX] to introduce PCIe Gen 3 products at the same time as market-leading CPU, chipset, and graphics suppliers," said David Raun, VP of marketing and business development at PLX.

Graphics chips are expected to be the first to use the new interconnect, perhaps as early as next year, because faster I/O translates directly into better graphics performance on visualization applications and games. Servers are expected to follow, perhaps sometime in 2012, using the interconnect to handle multiport 10GbE networking cards, high-speed Infiniband and storage links such as 6Gbit/s serial attached SCSI.

"All of these technologies can consume four to eight channels of PCIe 8GT/s links," said Mike Krause, an interconnect specialist in Hewlett-Packard's x86 server group and a member of the PCI SIG. "The economy will certainly play a role in how fast PCIe 3.0 is deployed, but the 2011-2013 time frame has been put forth by the PCI SIG as a likely adoption for multiple market segments," he added.

The PCI SIG is still debating two new extensions for PCIe 3.0 proposed by Advanced Micro Devices and HP, although Krause would not disclose details. If they are adopted, chipmakers might not incorporate the extensions in their products until they field a second wave of PCIe 3.0 components, he said.

In August, the PCI SIG reported it was still working on a version 0.5 of the Gen 3 spec. At that time engineers were still working on electrical validation, trying to determine if version 3.0 could handle the full 20-inch length of PCI and be backward compatible with version 1.0.

- Rick Merritt
EE Times

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