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LatticeSC/M DDR/DDR2 SDRAM memory interface user's guide

Posted: 16 Jun 2009 ?? ?Print Version ?Bookmark and Share

Keywords:memory interface? SDRAM? DDR2 DDR?

FPGA logic designers are often faced with the need to communicate with external memories, and applications are requiring increasingly large I/O channel bandwidths. In response to these demands, the industry has defined several new memory devices with their associated protocols (e.g. QDR-SRAM, DDR/DDR2 SDRAM, RLDRAM), each being optimized for a particular segment of the high-bandwidth market.

This user's guide discusses a memory interface for a Double-Data-Rate SDRAM (DDR/DDR2 SDRAM) implemented in the LatticeSC and LatticeSCM FPGAs. LatticeSC/M FPGAs support data rates for individual DDR2 devices and SODIMM modules at rates up to 667Mbit/s for the embedded MACO block and rates up to 533Mbit/s for soft IP cores.

View the PDF document for more information.





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