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Low-power FPGAs come with security features

Posted: 02 Jul 2009 ?? ?Print Version ?Bookmark and Share

Keywords:low power FPGA? feature security? static power 0.25W?

Altera Cyclone III LS FPGAs

Altera Corp. has announced the Altera Cyclone III LS FPGAs, a low-power FPGA family with security features. These devices offer 0.25W of static power for 200K logic elements. The Cyclone III LS FPGAs, which are shipping now, target power and board-space-sensitive applications in all market segments including military and industrial.

The Cyclone III LS FPGA's security features include a comprehensive information-assurance design suite that offers anti-tamper, design-security and design-separation capabilities. To protect highly sensitive information, the Cyclone III LS FPGAs' anti-tamper features include JTAG port protection, tamper monitoring and cyclical redundancy check (CRC). Offering another layer of protection, these devices feature an industry-standard AES 256bit encryption key for design security. Where size, weight and power requirements are crucial, the design-separation feature of the Cyclone III LS FPGA enables high-assurance and industrial-safety applications in a single chip through logic, routing and I/O bank separation.

Cyclone III LS FPGAs allow a single-chip solution for next-generation military applications such as SDR, crypto-subsystems and crypto modernization equipment where long battery life, density at the lowest power, and small board space are required. The additional security features of the Cyclone III LS FPGAs give designers of secure communications applications the assurance that their information will be protected with anti-tamper technology.

These FPGAs' features also provide the optimal solution for industrial applications, specifically motion control, Industrial Ethernet and industrial safety. Using the design-separation feature lowers system power and increases integration while offering design redundancy for safety-critical applications.

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