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SRAMs designed for next-gen comms network

Posted: 10 Jul 2009 ?? ?Print Version ?Bookmark and Share

Keywords:SRAM? communication network? 72Mbit DDR?

Renesas Technology Corp. has announced the 72Mbit Quad Data Rate II+ (QDR II+) and DDRII+ high-speed SRAM product family for use in high-end routers and switches in next-generation communication networks.

According to the company press release, these SRAM products achieve the industry's fastest level operating speed and are compliant with the QDR Consortium industry standard. Additionally, this release also includes 72Mbit QDRII and DDRII SRAM devices. The full range of devices, consisting of multiple speeds and configurations, will be available from August 2009 sequentially in Japan.

These new products offer operating speeds of 533MHz for the QDRII+ and DDRII+ SRAM, and 333MHz for the QDRII and DDRII versions. For these products, Renesas increased the operating speeds while maintaining low-voltage operation by using the 45nm fabrication process. The QDRII SRAM products achieve the industry's highest operating speed level of 333MHz, and the QDRII+ SRAM products also provide the industry's highest operating speed level of 533MHz. These devices can support high-speed processing for packet look-up and packet buffer applications in high-end routers and switchers that support 10G, 40G and beyond multilayer communication systems.

Renesas will provide products that support three data I/O widths (9-, 18- or 36bits) and two burst lengths (2 or 4 words). In addition, Renesas will also provide products that feature a built-in on-die termination function that reduces the signal quality degradation that can occur during high-speed operation.

With the ever-growing popularity of the Internet, transmission speeds and the amount of traffic being sent to communication equipment continue to increase, with data rate speeds now exceeding 40Gbit/s. Checking data destinations and managing data packet traffic in high-end networking equipment is driving the demand for high-density memory capable of high speeds. Furthermore, the complexity of data continues to increase with video, voice and data applications, requiring even larger memory capacities.

These products are available in all combinations of burst lengths and bit widths, and the standard High-Speed Transistor Logic interface is used for ultrahigh-speed synchronous SRAM. The package used is a 165-pin plastic FBGA with a 15mm x 17mm size and is suitable for high-density mounting. These products are RoHS-compliant, and lead-free versions are also available. The QDR pin configuration can support migration to densities up to 288Mbits in the future. In addition, FBGA package products support the IEEE standard test access port and boundary scan architecture (IEEE Std 1149.1-1990) that allow interchange connection checking during module mounting to be conducted at the board level.





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