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Chartered expands 65nm foundry portfolio

Posted: 14 Jul 2009 ?? ?Print Version ?Bookmark and Share

Keywords:foundry? RF processes? 65nm technology?

Expanding its foundry portfolio, Singapore's Chartered Semiconductor Manufacturing Pte. Ltd has rolled out separate low-power and RF processes, based on its 65nm technology.

In the first announcement, Chartered rolled out the general availability of an enhanced version of its 65nm, low-power process dubbed 65nm LPe. The process is said to employ leakage-reduction techniques to improve SoC standby power consumption by up to 50 percent. The process improves the performance-to-leakage ratio within the pMOSFET. Given the same Ion the Ioff current is reduced by a magnitude of 20x, according to Chartered.

Chartered's new process features a core 25 angstrom transistor oxide with three voltage options (standard Vt, low Vt, high Vt). The high Vt option offers the lowest leakage at 0.01nA/?m and 0.007nA/?m for the NMOS and PMOS transistors, respectively.

Two thick gate oxides are available: a 32A device for 1.8V; and an IP-enabled 2.5V 52A device that is also useable for 1.8V and 3.3V applications by varying the channel length.

The back-end-of-line metal implementation supports up to nine layers of copper to optimize die size and efficiency. Manufactured on rotated substrates, the 65LPe process benefits from the an increase in the pMOSFET hole mobility and saturation velocity without affecting the nMOSFET.

A full suite of IP is available for the new process from leading suppliers, including Analog Bits, Aragio Solutions, ARM, Cosmic Circuits, Denali, Synopsys, True Circuits and Virage Logic.

''Today's high-volume mobile applications require highly optimized silicon solutions that operate in an extremely power-efficient manner, but don't compromise performance or functionality," said Brian Klene, VP of product marketing at Chartered, in a statement. ''Our 65nm LPe process has been developed specifically with extended battery life in mind, with optimizations made to the process itself and our ecosystem of design support to improve efficiency significantly.''

In the second announcement, Chartered rolled out a 65nm RF platform geared for developers of single-chip RF products. The process, jointly developed with IBM Corp., is based on Chartered's 65nm LPe technology.

The RF platform is aimed to reduce the time, cost and risk associated with developing single-chip solutions that incorporate RF.

It includes an IBM RF physical design kit (PDK), which is available from Chartered. The PDK enables a methodology, based on a parameterized cell (p-cell) design approach that allows designers to tune RF components in a wide variety of ways.

In addition, a spectrum of IP support for RF applications is available for the 65nm RF platform. This includes silicon tested RF subsystems for WiFi, WiMax, and GPS. It also has a host of industry standard interfaces (mDDR/DDR/DDR2, USB 2.0, PCI Express, SATA II and LVDS); and functional analog/mixed-signal subsystems (Analog front-end, audio codec, Video ADC/DAC, PLL/DLL and baseband DAC/ADC).

Through Chartered's participation in and support of the WISPA consortium, the 65nm RF process is backed by RF and SoC design services companies that can facilitate IP customization and software development via reference boards. WISPA participants Socle Technology Corp. and Catena have worked together to develop a modular platform consisting of RF and baseband functions centered on hardened ARM9 and ARM11 microprocessor cores.

- Mark LaPedus
EE Times





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