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PCIe 3.0 gears for 8GHz by next year

Posted: 20 Jul 2009 ?? ?Print Version ?Bookmark and Share

Keywords:PCIe? interconnect? PCIe 3.0 8GHz? Ethernet?

PCI Special Interest Group has announced that the final specification for PCIe 3.0 will be released by June 2010. PCI SIG members also provided more detail about the spec, suggesting some of the challenges companies will have implementing the 8GHz interconnect.

Meanwhile, engineers are also working through new challenges using the virtual I/O standards the PCI SIG released at its conference last year. And others are working on an updated version of a PCIe cable supporting data transfers at up to the 5GHz rate of PCIe 2.0.

"The big news is PCI Express version 3.0 will be available in the first half of next year," said Al Yanes, president of the PCI SIG in a press briefing here.

The new interconnect is expected to start shipping in systems in 2011. It initially will be used for bandwidth-hungry graphics chips in high-end desktops and in servers using multiport 10Gbit Ethernet and 8Gbit Fibre Channel cards.

The spec is expected to be in a version 0.7 this quarter. From that point, engineers will be running simulations and test chips to validate theoretical models of the technology. A separate test specification is also in the works.

When the work is complete, the 8GHz interconnect is expected to be compatible with the previous 2.5-and 5GHz versions and use the same connectors. It also is expected to support the existing PCIe bit-error rates and the reach of up to 20 inches and two connectors for servers.

The SIG chose 8GHz rather than 10GHz for PCIe 3.0 as a power saving measure. The additional equalization required to hit 10GHz would have required "exponentially" more power, Yanes said.

"The power shot off the roof," in 10GHz PCIe simulations, he said.

That decision forced developers to use a more aggressive 128b130b scrambled encoding scheme to maintain a doubling of throughput for the new generation interconnect to a Gbyte/second per lane in a single direction. The new encoding approach has just 1.6 percent overhead on data transmissions compared to 20 percent for the existing 8b10b encoding scheme.

8GHz challenges
Supporting the new encoding scheme and maintaining backward compatibility to the earlier versions of the spec are the two chief implementation challenges engineers face with PCIe 3.0, Yanes said.

Indeed, one test engineer said it is requiring significantly more gates in the FPGA his company uses in a protocol analyzer. For example, just finding the start of a new byte is a more complex task, he said.

Supporting the new and old encoding schemes may force some designers into using two PHY cores arbitrated by a switch. Products will at least have to support two phase-lock loops to handle the 8- and 5-/2.5GHz clocking.

Thus PCIe 3.0 chips are expected to require at least a 65nm process technology. "We don't envision people using 90nm," Yanes said.

It's not clear yet what levels of equalization the new spec may require. Gennum Corp. announced earlier this year it is licensing silicon controller and physical-layer blocks for PCIe 3.0 that use five-tape decision feedback equalization.

Motherboard makers will still be able to use four-layer boards for PCIe 3.0 designs. However they may need to adopt new trace routing techniques and face impedance margins tighter than today's 85? limits.

Both PCIe versions 3.0 and an updated version 2.1 support a handful of new features. They include atomic operations, TLP processing hints and ID-based ordering capabilities that will be particularly helpful for handling parallel operations in multicore systems.

Yanes said he was not aware of any more aggressive features in the works for PCIe to support emerging parallel programming constructs still in an early research phase. One source said Advanced Micro Devices and Hewlett-Packard have proposed multiplexing extensions for 3.0, but the proposal has not been released or voted on by the PCI SIG board yet.

Synopsys Inc. also announced it has released PCIe 3.0 controller, physical layer and verification blocks to early customers. Cadence and nSys Design Systems also announced verification IP for PCIe 3.0. For its part, Synthesis Research Inc. announced an integrated test bench to handle transmitter and receiver testing for the earlier 2.5- and 5GHz versions of PCIe.

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