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Power to take center stage at DAC

Posted: 28 Jul 2009 ?? ?Print Version ?Bookmark and Share

Keywords:low-power design? DAC show? multicore? EDA?

As has been the case for the past several years, low-power design is expected to emerge as one of the central themes of the 46th Design Automation Conference (DAC).

Power, arguably today's No. 1 headache for designers, will be the theme of workshops, tutorials, meetings, presentations and technical tracks. An unknown number of products will be introduced next week that focus in part or whole on helping designers create more power efficient designs.

Executives at EDA vendors and other firms agree that the focus on low power is warranted. At advanced nodes, designers are grappling with huge challenges associated with leakage power, not to mention continuing to deal with competing power formats.

"Low power is one of the biggest challenges that designers face today," said Cary Chin, director of technical marketing for low-power solutions at Synopsys Inc.

Leakage power concerns at the 90nm node and below, combined with the demand for more functionality on portable devices, continue to push demand for techniques that lower both static and dynamic power consumption, Chin said. Below 65nm, techniques such as power shutdown, multi-voltage design and even dynamic frequency and voltage control are becoming mainstream, according to Chin.

Designers working on ICs for wireless and handheld markets started relying heavily on techniques such as clock-gating, multi-voltage threshold swapping and multi-voltage domains at the 65nm node, said Dan Blong, a marketing executive from Magma Design Automation Inc.'s design implementation business unit.

"At 40nm and below, where leakage power is a dominant factor, designers across most market segments are focused on addressing power through better voltage domain management at the block level and careful management of clock trees through the chip," Blong said.

Addressing leakage problems
Designers are taking even more dramatic steps to combat leakage at the advanced nodes, according to Mark Throndson, director of product marketing at IP provider MIPS Technologies Inc. "We're seeing a great amount of interest in solutions for reducing leakage power in our multicore products through solutions like dynamic core shutdown," he said.

Since dynamic power is proportional to the voltage squared, designers are focusing more on using multiple voltages and multiple voltage domains in their designs, said Barry Pangrle, a solutions architect for low power design and verification at Mentor Graphics Corp. Portions of the design now must operate in multiple modes (drowsy, sleep, active, turbo) where the voltage and clock frequencies are tailored to be as energy efficient as possible while simultaneously delivering the performance necessary for that given mode, he said.

"In cases where a portion of the design's functionality isn't needed, the power can be shut off to further reduce the leakage power," Pangrle said.

Power has become an intricately interwoven element of the design closure process, a multi-faceted challenge that becomes more daunting at the 40- and 32nm nodes, according to Steve Carlson, VP of marketing for front-end design at Cadence Design Systems Inc.

Exacerbating this is the more prominent role of analog content in advanced designs, Carlson said.

"Most advanced node designs are aimed at high-volume applications that require significant analog-functional content. The interlock of all these aspects of design is really the crux of the challenge of today's design teams," Carlson said. "The solution must be rooted in a holistic approach that brings together the design process, the closure criteria, the underlying infrastructure and the ecosystem."

Still another challenge in the realm of power is that, since low-power designs tend to have a poor SNR, maintaining reliable system operations becomes more challenging, said Nhat Nguyen, a senior engineering manager at memory IP vendor Rambus Inc.

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