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Utilizing extra FC credits for PCI Express inbound posted memory write transactions in PowerQUICC III devices

Posted: 17 Aug 2009 ?? ?Print Version ?Bookmark and Share

Keywords:PowerQUICC? PCI express? memory?

As described in the PCI Express chapter of the reference manual, current Power QUICC III devices feature Posted Header (PH) of 4 and Posted Data (PD) of 64 as FC credits initially advertised for PCI Express inbound memory write transactions, where 64 PD credits are equivalent to total data payloads of 4 transaction layer packets (TLPs) with 256byte each as the maximum payload size.

These initial FC credits advertised are plenty for all PCI Express x1, x2 and x4 applications. When x8 link width is implemented, some performance demanding PCI Express application might need some extra FC credits (PH and PD) for inbound posted memory write transaction.

There is currently some hidden receiver buffer space available to satisfy this demand. When the SRIO interface of a Power QUICC III device is not enabled on the same Serdes port where x8 is selected as PCI Express link width, some hidden buffer space can be made available to the PCI Express receiver. This allows the x8 PCI Express interface to advertise and utilize 6 as PH and 96 as PD (equivalent to the total payload of 6 transaction layer packets (TLPs) with 256byte each as the maximum payload size), therefore makes the aforesaid demand possible.

The following sections describe the detailed procedure to follow when enabling the extra receiver buffer space is desired. Two service registers are involved to override the default posted FC credit initially advertised.

This application note explains the procedures to utilize the extra FC (flow control) credits for PCI Express inbound posted memory write transactions, which is currently a hidden feature for all of the x8-capable Power QUICC III devices.

View the PDF document for more information.

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