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IBM zooms past multicore server rivals

Posted: 31 Aug 2009 ?? ?Print Version ?Bookmark and Share

Keywords:processor? multicore? IBM server? DDR3?

AMD's 12-core bet
For its part, AMD is stealing a page from archrival Intel by building its 12-core Magny-Cours out of two of its six-core Istanbul dice. Intel released some of its early multicore chips using two die sharing a single front-side bus and external memory controller.

AMD is improving on Intel's approach by providing on each die a two-channel DDR3 memory controller and four coherent HyperTransport 3 links. As a result, data in a two-chip system can travel between any two cores in a single hop and in two hops in a four-chip server.

"Basically we are taking a leaf from [Intel's] book but doing it differently, said Pat Conway, principal member of technical staff at AMD who said to expect use of MCMs in the company's future CPUs.

The move to 12 cores also forced an upgrade of AMD's memory protocols. Rather than broadcast cache coherency checks across all cores, Magny-Cours carves out a megabyte of its 6Mbyte cache to hold a table that tracks all cached data.

The technique, used on all future CPUs and activated by a BIOS setting, can reduce memory latency in servers from 120ns to 50ns, boosting performance. "There is a small negative impact in the L3 hit rate going from 6- to 5Mbyte cache, but the system level benefit in reducing memory latency and increasing bandwidth makes it a clear net win," Conway said.

Indeed, researchers see work on cache coherency protocols as one of the key planks for the many-core parallel processors expected in the future.

The next big turn of the screw for AMD will involve plugging its next-generation Bulldozer core into a Magny-Cours design. The new core expands what has been the single-threaded nature of the AMD cores "in a different fashion than Hyperthreading," said Conway, referring to Intel's method for supporting two threads on a core.

AMD's Magny-Cours server CPU consists of two six-core die. Source: AMD (Click on image to enlarge.)

Intel will describe its Xeon 7500, the follow on to the Series 5500 aka Nehalem server chip that debuted earlier this year. The new design sports four memory controllers and is geared for systems using as many as four processors.

"It's a very impressive chip, but I don't think it's going to have the memory bandwidth of Power7 or as large an L3 cache," said Brookwood.

Meanwhile, Sun will describe Rainbow Falls, the next version of its multi-threaded Niagara processor. It may mark one of the first new disclosures from the company which has gone quiet while it waits for the European Commission to review its merger with Oracle Corp.

"The deal was approved by stockholders two months ago, and they still can't say anything" due to the EC review, said Brookwood. "It's just tragicby the time the dust settles there may not be much of a Sun hardware business left," he said.

- Rick Merritt
EE Times


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