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Singapore launches 3D TSV consortium

Posted: 11 Sep 2009 ?? ?Print Version ?Bookmark and Share

Keywords:3D TSV consortium? Singapore IC industry? wafer manufacturing? through-silicon via?

The Institute of Microelectronics (IME), a research institute of Singapore's Agency for Science, Technology and Research (A*STAR), has announced a 3D through-silicon via (TSV) consortium to boost next-generation 300mm wafer manufacturing capability. This is aimed to support the Singapore semiconductor industry to meet technology and product needs.

The consortium is a national initiative and is supported by the Singapore Economic Development Board (EDB) and A*STAR. IME is teaming up with A*STAR's Institute of High Performance Computing (IHPC) and Nanyang Technological University (NTU) in the consortium, which consists of two phases with a duration of eighteen months for each phase. IME is leading Phase 1 of the consortium with participating companies including Chartered Semiconductor Manufacturing Ltd, STATS ChipPAC Ltd and United Test and Assembly Center Ltd. The consortium will also leverage strategic materials and equipment suppliers for support in its endeavors.

The goal of Phase 1 is to establish TSV design and processes for 200mm and 300mm TSV wafers 3D IC assembly, and train a pool of skilled personnel in the semiconductor supply chain companies to support manufacturing of new products with 3D TSVs. Phase 2 will demonstrate the integration of fully functional mobile devices with TSV on a 300mm wafer process line.

Beyond Moore's law
"The launch of this consortium is timely as the semiconductor industry is grappling to find solutions to extend the limit of transistor scaling beyond Moore's Law. TSV opens up new possibilities to add complex and multi-functional features to electronic devices by allowing integrated circuits or packages to be stacked vertically," said Dim-Lee Kwong, executive director of IME. "Over the last few years, IME has established deep competencies and process capabilities for TSV carriers. What is unique in this consortium is that we are able to gather key companies across the Singapore semiconductor supply chain to establish cost-effective TSV process integration and manufacturing capability on 300mm wafers to help accelerate the industry adoption of 3D ICs with TSV."

Raj Thampuran, executive director of IHPC, added, "IHPC is delighted to be a part of this consortium. Modeling and simulation capabilities will certainly help to predict and optimize the performance in the complex design of the TSV carriers."

Kam Chan Hin, chair of the School of Electrical and Electronic Engineering at NTU, noted, "This consortium has also provided Nanyang Technological University a platform and new opportunity to work more closely with our partners to bring academic research to the industry."

Commenting on the value creation of R&D to industry, Chong Tow Chong, executive director of A*STAR's Science and Engineering Research Council, said "One of A*STAR's objectives is to promote R&D in fields that add value and grow the Singapore's manufacturing industry. This consortium exemplifies how A*STAR research institutes work with companies and institutes of higher learning to identify and develop next-generation capabilities and technology to enhance the competitiveness of the semiconductor industry in Singapore."

Damian Chan, director of the electronics cluster of the Singapore EDB, said "Our vibrant semiconductor ecosystem consisting of IC design, wafer fabrication, advanced assembly and test, and supported by a strong base of suppliers offers a "Plug and Play" environment. The concentrated ecosystem allows semiconductor companies to easily find their business partners while enjoying access to the international market." He added that "R&D is the key to strong growth in the future. This industry-public research collaboration is a unique opportunity for global players such as Chartered, STATS ChipPAC and UTAC to leverage on each other's unique expertise and co-develop this emerging technology to address the needs of the industry."

"Chartered understands that our customers need technology and solutions that address their requirements in performance, cost and scaling. The 3D TSV Consortium allows Chartered to focus on our core competency in TSV silicon integration while leveraging the expertise of our partners in material research, design, bonding, packaging and testing. The result is a proven 3D TSV infrastructure from design to tested package," said Liang-Choo Hsia, senior VP of technology development at Chartered.

"We believe the depth of expertise at IME and the consortium members, combined with the knowledge we have on driving integration technology and flexibility at the silicon level will provide important momentum in developing 3D TSV technology into high volume IC packaging solutions. Our involvement with the 3D TSV consortium will complement the research and development activities we have been working on in advanced wafer integration technology," said Il Kwon Shim, VP of technology innovation at STATS ChipPAC.

"The new capabilities acquired from this strategic consortium will help UTAC increase our service offerings to our customers. The innovative capabilities and technologies will provide greater efficiencies in our delivery of customer focused solutions," said Anthony Sun, group VP of R&D of UTAC.





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