Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Manufacturing/Packaging

Panasonic, Renesas run 28nm development line

Posted: 02 Oct 2009 ?? ?Print Version ?Bookmark and Share

Keywords:Panasonic-Renesas SoC development? 32nm process? semiconductor? 300mm wafer?

Panasonic Corp. and Renesas Technology Corp. will concentrate their joint development functions for 28nm process SoCs at the Renesas Naka site in Hitachinaka City, Ibaraki Prefecture, Japan.

Both have agreed on the joint development of next-generation SoC technologies in 1998, even before Renesas was formed. They developed semiconductor process technologies for the 90-, 65-, 45- and 32nm generations at the Renesas Kitaitami site in Itami City, Hyogo Prefecture. One result of this joint effort, which was achieved in October 2008, was the development of interconnect technology using both transistor technology that has a metal/high-k gate stack structure and ultralow-k materials for the 32nm system SoC process and acquiring a firm target date for its application in mass production. Also, in July 2009, this collaboration completed development of an SRAM cell using a metal/high-k gate stack structure for the 28nm process. Now, based on these results, the two companies will start operation of that line to carry out joint development of full integration technology using 28nm process manufacturing technologies in the 300mm wafer development line newly installed at the Renesas Naka site.

In the development line at the Naka site, the two companies have installed new production equipment in addition to having transferred part of the development line equipment from the Renesas Kitaitami site. By carrying out this development in the wafer size that will actually be used in mass production, the two companies are aiming to achieve a smooth transition to mass production and reduce development costs and time. This will improve development and production efficiency.

The companies will start operating a 28-/32nm process development line this October 2009. By concentrating their joint development functions on the Naka site's 300mm wafer line, the companies target the start of mass production in the near future.

Article Comments - Panasonic, Renesas run 28nm developm...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top