Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Assembly guidelines for Dual Power56 Packaging

Posted: 26 Oct 2009 ?? ?Print Version ?Bookmark and Share

Keywords:Packaging Power56 assembly? processing soldering? assembly dual power56?

The Fairchild Dual Power56 package is based on Molded Leadless Packaging (MLP) technology. This technology has been increasingly used in packaging for power-related products due to its thermal performance with large thermal pads in the center of the package, which solder directly to the printed wiring board (PWB). Modularity in package designsingle and multi-die packagesis within the capability of MLP technology.

The Dual Power56 has two large die attach pads allowing direct soldering to the PWB for best thermal and electrical performance. These two pads are the co-packaged high and low side MOSFETs. The Dual Power56 is designed to be used in high current synchronous buck DC/DC circuits, saving board space and component count by integrating the high and low side MOSFETs into one package.

This application note focuses on the soldering and back end processing of the Dual Power56.

View the PDF document for more information.

Click here to view related datasheets.





Article Comments - Assembly guidelines for Dual Power56...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top