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Techniques for evaluating deterministic jitter

Posted: 23 Oct 2009 ?? ?Print Version ?Bookmark and Share

Keywords:deterministic jitter? PLL clock generators? power supply noise?

Clock generators that employ PLLs are widely used in network equipment for generating high-precision and low-jitter reference clocks, or for maintaining a synchronized network operation. Most clock oscillators give their jitter or phase noise specification using an ideal, clean power supply. In a practical system environment, the power supply can suffer from interference due to on-board switching supplies or noisy digital ASICs. To achieve the best performance in a system design, it is important to understand the effects of such interference.

This article discusses the effects of power supply noise interference on PLL-based clock generators and describes several measurement techniques for evaluating the resulting deterministic jitter (DJ). Relationships are derived outlining how frequency domain spur measurements can be used to evaluate timing jitter behavior. Laboratory bench test results are used to compare the approaches and demonstrate how to reliably assess the power-supply noise rejection (PSNR) performance of a reference clock generator.

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