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Six-core DSP achieves 3GHz at 0.15mW/MIPS

Posted: 07 Dec 2009 ?? ?Print Version ?Bookmark and Share

Keywords:DSP? multicore processor? memory controller?

TMS320C6472 DSP

Texas Instruments Inc. has released TMS320C6472, claimed to be the most power efficient, six-core DSP targeted at process-intensive applications requiring low power consumption. To help evaluate the performance of the C6472 devices more easily and affordably, TI is also offering a multicore processors evaluation module (EVM), the TMDXEVM6472, for $349.

With the C6472, TI has broken the power performance barrier by fully optimizing the device for applications where performance per watt is a critical requirement. The C6472 DSP touts the lowest power consumption with the highest processing performance of any multicore DSP with the total of 3GHz performance in the market, performing at 3.7W performance and 0.15mW/MIPS.

TI's power-efficient C6472 was designed to support applications that drive many channels, demand maximum performance density and for which designers must have access to sophisticated functions. Additionally, many applications utilizing the C6472 will not require any external memory, further improving the power profile and cost effectiveness of the device. These devices are suitable for markets such as high-end industrial, test and measurement, communication, medical imaging, high-end imaging and video, and blade server. TI provides extensive support for the C6472, including an evaluation module, robust software libraries and a third-party ecosystem, to further facilitate the process of writing code that runs optimally on multicore devices.

C6472 DSP features six high-speed C64X+ DSP cores running at 500MHz, 625MHz, 700MHz, and fully backward compatible with other C64X DSP cores. The device also packs up to 4.2GHz/33600 MMACs and 4.8Mbyte on-chip L1/L2 RAM. The C6472 also offers optimized DSP architecture that maximizes subsystem performance on a chip. One of the advantages of this architecture is that in addition to dedicated L1 and L2 memory to each core, the C6472 features 768Kbyte shared L2 program/data memory and a shared memory controller to facilitate high efficient and flexible inter DSP core communications.

In addition, the device contains rich device peripherals including Gigabit Ethernet, serial RapidIO, DDR2, telecom serial interface port, host port interface, Utopia, I?C bus and GPIO.

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