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Processors boast efficient multiprotocol processing

Posted: 14 Dec 2009 ?? ?Print Version ?Bookmark and Share

Keywords:processor? processing multiprotocol? multicore?

P1021 processor

Freescale Semiconductor is offering the QorIQ P1012/P1021 family, with the QUICC Engine multiprotocol technology, delivering high-performance, low-power migration path to all-IP environments for customers using legacy multiprotocol interfaces.

Most embedded multicore processors integrate general-purpose CPUs not optimized for data-plane tasks, thus requiring more or faster CPUs to deliver the same level of performance for multiprotocol processing.

The QorIQ P1012 and P1021 processors deliver highly-efficient multiprotocol processing by integrating the latest QUICC Engine technology alongside one or two 800MHz cores based on Power Architecture technology.

The combination of the QorIQ and QUICC Engine technologies enables the devices to provide both data- and control-plane processing, which eliminates the need for separate FPGAs or ASICs.

The new products are pin-compatible with existing QorIQ P1 and P2 products, as well as software-compatible with several Freescale PowerQUICC II Pro and PowerQUICC III processors, including the MPC8323, MPC8358, MPC8360 and MPC8569 devices.

This compatibility preserves software investments and delivers a range of price and performance options for a broad spectrum of wireless, wireline and industrial applications.

In addition, the P1012 and P1021 processors can be paired with Freescale's VortiQa application software to rapidly create performance-optimized SMB gateway products. The new processors support legacy interfaces and protocols such as T1/E1, xDSL, ATM, HDLC and 10/100/1000 Ethernet for applications including multiservice routers, SMB gateways and IP-PBX equipment.

The programmability of the QUICC Engine technology also enables industrial interfaces and protocols, providing the flexibility to support additional applications with a common platform.

Based on 45nm process technology, the processors incorporate large, high-performance L2 cache memories and feature support for cost-effective and power-efficient DDR3 memory, thus allowing customers to further reduce overall system cost.

The devices also integrate SGMII, USB 2.0 and PCIe interconnect technologies. Development boards and third party enablement tools are available for the P1012 and P1021 devices to streamline development. Both processors are expected to sample to select customers in January 2010, with broad sampling planned for Q2 10.

- Julien Happich
EE Times Europe

For application notes on processors click here.

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