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IBM details 3D IC design challenges

Posted: 17 Dec 2009 ?? ?Print Version ?Bookmark and Share

Keywords:3D? through-silicon via? chip design?

Spotlight is now on the 3D chip design.

IC makers are exploring the possibly of stacking current devices in a 3D configuration. Experts define a true 3D package as one that stacks various chips vertically and then connects them by deploying through-silicon vias (TSVs). The aim is to shorten the interconnections between the chips, reduce die sizes and boost device bandwidths.

So far, chipmakers are shipping limited 3D devices based on TSVs, mainly CMOS image sensors, MEMS, and, to some degree, power amplifiers. But for years, IBM, Intel and others have been looking at stacking microprocessors, memory and other functions using TSV technology.

IBM, for example, has produced a power amplifier based on TSVs. It has also announced several R&D processor projects with 3D designs. A production-worthy device is not expected until 2012.

Rival Intel has not found a "killer application" for 3D.

Indeed, chipmakers have experienced stumbling blocks in that arena. According to John Knickerbocker, a distinguished engineer from IBM Corp., here's five challenges for 3D devices based on TSVs:

1. Lack of EDA design tools. "There is room for growth in design tools."

2. Complexity of designs. The industry is making 3D devices with relatively few TSVs, but the key is to make parts "with thousands of TSVs." Drawing heat out of such a complex 3D design is also a challenge.

3. Integration of assembly and test. It's unclear if 3D chips based on TSVs will be produced by the IDMs, foundries or IC-assemblers, but one thing is clear: "Test is a challenge for everyone."

4. Heterogeneous system integration. The challenge is to integrate different chipssuch as "RF, memory and the MPU"in one part.

5. Standards. SEMI has standards. Sematech has different specs. Others are moving in their own directions.

- Mark LaPedus
EE Times





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