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Implementing PLL reconfiguration in Stratix III devices

Posted: 23 Dec 2009 ?? ?Print Version ?Bookmark and Share

Keywords:devices Stratix? PLL reconfiguration? PLL?

PLLs use several divide counters and different voltage controlled oscillator taps to perform frequency synthesis and phase shifts. In Stratix III PLLs, you can reconfigure the counter settings and dynamically phase-shift the PLL output clock. You can also change the charge pump and loop filter components, which dynamically affect the PLL bandwidth. You can use these PLL components to update the clock frequency, PLL bandwidth and phase shift in real time, without reconfiguring the entire FPGA.

Applications that operate at multiple frequencies can benefit from PLL reconfiguration in real time. PLL reconfiguration is also beneficial in prototyping environments, allowing you to sweep PLL output frequencies and adjusting the clock output phase at any stage of the design. For instance, a system generating test patterns is required to generate and transmit patterns at 50MHz or 100MHz, depending on the device under test. Reconfiguring the PLL components in real-time allows you to switch between two such output frequencies within a few microseconds. You can also use this feature to adjust clock-to-out (tCO) delays in real time by changing output clock phase shift. This approach eliminates the need to regenerate a configuration file with new PLL settings.

This application note describes the flow for implementing PLL reconfiguration in Stratix III devices.

View the PDF document for more information.

Click here to view related datasheets.





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