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Anti-tamper protection for Cyclone III LS devices

Posted: 06 Jan 2010 ?? ?Print Version ?Bookmark and Share

Keywords:anti-tamper protection? Cyclone III devices? design platform?

This application note presents a design platform that integrates the various Cyclone III LS security features with an external MAX II device as a configuration manager.

Cyclone III LS devices extend the Cyclone architecture to include higher density, higher memory, smaller packages, and security features to protect your intellectual property (IP). These FPGAs are the first devices to implement a suite of security features at the silicon, software, and IP level on a low-power, highly-functional device platform.

The suite of security features in Cyclone III LS devices consists of Design Separation and the following Silicon security features:
? internal oscillator;
? 256bit advanced encryption standard (AES) bitstream encryption;
? JTAG port protection;
? Zeroization (active clear);
? Cyclical redundancy check (CRC).

The Cyclone III LS device family offers both passive and active resistance against IP theft. AES bitstream encryption and JTAG port protection provide a passive layer of resistance against theft of confidential design files. The CRC error detection feature and an internal oscillator allow you to create an application that actively monitors designs for tamper evidence during operation.

The Cyclone III LS security features allow you to develop a secure configuration manager (an application to initialize the device to a known state) to enable passive protection against theft, and to actively monitor the design to ensure that the target operational environment does not deviate.

The configuration control and management presented in this application note form a design template that provides the standard set of security functions common to most Cyclone III LS designs.

View the PDF document for more information.

Click here to view related datasheets.





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