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Targeting small delay defects

Posted: 13 Jan 2010 ?? ?Print Version ?Bookmark and Share

Keywords:delay defect? quality of test? ATPG delay defects?

In the nanometer technology era, as the designs going further below 65nm, maintaining quality of test is a big concern in the test community. Test engineers are facing new test challenges at lower geometries and the small delay defects are one of them, which pose a serious concern for maintaining good DPM levels.

The lower technology nodes are more susceptible to delay defects. At such lower nodes, the process needs to be accurate. Inaccuracy may manufacture transistors that are slower in switching and operation. Such small delay defects may not show up in normal transition testing but appear when a test is targeted on timing critical paths. Thus, to maintain the quality of test for the reasonable DPM levels, more and more test engineers are looking to target small delay defects with ATPG.

TestKompress from Mentor Graphics is currently the most widely used EDA tool in the industry for test compression and ATPG. It offers two strategies for targeting small delay defect: path delay testing and timing-aware ATPG. In the following sections, we�ll explore the usage of both the techniques and also look at their pro's and con's.

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