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Freescale taps Mentor test, verification tech

Posted: 14 Jan 2010 ?? ?Print Version ?Bookmark and Share

Keywords:Mentor Freescale collaboration? DFM? verification? test analysis?

Freescale Semiconductor has chosen Mentor Graphics Corp. as a partner in the silicon test, yield analysis, and physical verification technology areas.

The collaboration enables Freescale's deployment of Mentor's Tessent and Calibre technologies covering design-for-test (DFT), physical verification and analysis, advanced resolution enhancement technologies (RET), and pre- and post-tapeout design for fabrication and manufacturability (DFM). The new technologies expand on the work of an existing collaboration between Freescale and Mentor for developing design flows and methods to improve design for manufacturing and silicon test capabilities.

"Freescale needs fast time-to-market, so we continue to invest significant resources to provide leading-edge capability throughout the design process," said Ken Hansen, VP and chief technology officer at Freescale. "Mentor's platforms are an integral part of Freescale's design flow, helping us provide silicon solutions that have a high degree of testability, reliability and manufacturability. We chose Mentor Graphics because of its leadership in the DFT, physical verification and DFM technology areas. This alliance enables Freescale to leverage one design flow to expand product functionality and serve multiple markets, while reducing our development cycle time."

"As a close partner with Freescale, we continue to see the benefits of working together on our common goal of achieving higher product functionality and reliability with accelerated time to market," said Joseph Sawicki, VP and general manager for the design-to-silicon division, Mentor Graphics. "Our work together helps Mentor provide technologies to Freescale that increase the performance and scalability of their most advanced SoC designs."





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