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ESD group urges more OEM support

Posted: 28 Jan 2010 ?? ?Print Version ?Bookmark and Share

Keywords:ESD? ESD specification? IC design?

An ad hoc group drafting guidelines for ESD specifications for ICs is hammering out a new campaign and white paper that hopes to get more of the systems-level community on board.

Many systems-level vendors are apparently uncomfortable with the new ESD guidelines for ICs set by the ad hoc group, dubbed The Industry Council on ESD Targets. The new and reduced ESD target levels, some systems houses argue, may impact the integrity of chip designs and overall product quality.

However, members of the council hope to set the systems-level community straight, saying the new ESD recommendations for ICs are proven and safe. The old ESD levels were overkill and added too much cost in overall IC design, the council claims.

The new ESD guidelines have been accepted by one industry standards body, the JEDEC Solid State Technology Association. But "there are still some misunderstandings and misconceptions" about the ESD guidelines in the systems community, said Charvaka Duvvury, a fellow at Texas Instruments Inc. and one of the industry's foremost experts on ESD.

Apparently, there is still concern about the reduced ESD target levels and the interaction between component- and system-level products. One of the group's next goals is to formulate a paper that aims to reduce or eradicate those misconceptions, Duvvury said.

Formed in 2006, the Industry Council on ESD Targets made headlines after proposing new and controversial ESD guidelines. The council consists of some 46 major companies, such as ADI, AMD, Freescale, Fujitsu, IBM, Infineon, Intel, LSI, Panasonic, NXP, Renesas, Samsung, TI and TSMC.

The group is addressing the growing ESD problem in electronics. "The age of electronics brought with it new problems associated with static electricity and electrostatic discharge. And, as electronic devices became faster and smaller, their sensitivity to ESD increased," according to a separate group called the ESD Association, a professional voluntary association.

"Industry experts have estimated average product losses due to static to range from 8-33 percent. Others estimate the actual cost of ESD damage to the electronics industry as running into the billions of dollars annually. The cost of damaged devices themselves ranges from only a few cents for a simple diode to several hundred dollars for complex hybrids," according to the ESD Association.

The Industry Council on ESD Targets, a separate and independent body of ESD experts, seeks to review the ESD robustness requirements of today's ICs. At first, the group moved to revise new and reduced levels for the human body model (HBM) and machine model (MM) qualification targets. The HBM test simulates the electronic transfer of a charge from a human to a device. The MM test simulates the transfer of a charge from a machine to a device.

When the new proposals appeared in 2007, some detractors suggested that lowering ESD levels was reckless, and could lead to catastrophic quality and reliability problems for semiconductors.

For years, chipmakers have developed digital IC products with on-chip ESD protection circuitry that supports the 2,000V level for the HBM and the 200V level for the MM. For years, chipmakers and their customers have accepted these ESD specifications as a standard on an ad hoc basis.

In 2007, the ESD council pushed the industry to lower the HBM level to 1,000V and the MM target to 30V. Then, in 2008, the council gained traction when JEDEC accepted those new guidelines. At that time, JEDEC announced the release of JEP 155, or "Recommended ESD Target Levels for HBM/MM Qualification," as written by the council. JEP 155 is not a hard and fast standard, but rather a recommendation for OEMS and chip makers.

"For more than 20 years, IC component level ESD target levels for both HBM (2kV) and MM (200V) have essentially stayed constant, with no focus on data to change these levels. Today's enhanced static control methods required by OEMs do not justify these higher HBM/MM levels as data will show in this document. ESD over-design to these levels in today's latest silicon technologies is increasingly constraining silicon area as well as performance, and is leading to more frequent delays in the product innovation cycle," according to the JEDEC-approved white paper from the council.

"Based on improved static control technology, field failure rate, case study and ESD design data, collected from IC suppliers and contract manufacturers, we propose more realistic and safe HBM/MM ESD target levels. These new levels (1kV HBM / 30V MM) are easily achievable with static control methods mandated by customers and with today's modern ESD design methods," according to the paper.

Even the new target levels for HBM and MM are "much more than really necessary," said Harald Gossner, senior principal engineer at Infineon Technologies AG and ESD expert. In reality, a 500V HBM is proven and safe, he said.


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