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New method enables pure graphene fabrication

Posted: 03 Feb 2010 ?? ?Print Version ?Bookmark and Share

Keywords:graphene IC? silicon wafer? carbon semiconductor?

Graphene wafer

100mm graphene wafer containing approximately 75,000 devices and test structures. Inset: Optical image of a single chip. Each small square pad on the chip is a mere 100?m. Devices were fabricated at the Penn State Nanofab, a facility of the Materials Research Institute.

Penn State researchers claim to have perfected a method of fabricating pure sheets of carbon semiconductor, called graphene, on 100mm (4-inch) wafers.

Penn State's Electro-Optics Center Materials (EOC) Division claims its process can be used to fabricate graphene chips that are 100-1,000x times faster than silicon, as well as enable more sensitive sensors, electronics, displays, solar cells, sensors and hydrogen storage devices.

Graphene is the crystalline form of carbon that self-assembles into two-dimension hexagonal arrays perfect for fabricating electronic devices. Unfortunately, when conventional deposition techniques are used with carbon to grow sheets much larger than one inch, they tend to degenerate into irregular graphite structures. But EOC researchers David Snyder and Randy Cavalero claim to have perfected a method called silicon sublimation which thermally removes silicon from silicon carbide wafers leaving behind pure graphene.

The team's technique uses a vapor transport furnace to encourage the silicon to migrate away from the wafer's surface, leaving behind the carbon in one- and two-atom-thick graphene films. While the process of silicon sublimation has been tried before to create graphene, the EOC is the first group claiming to have tweaking the process well enough to produce 4-inch wafers.

Sponsors for the research, the Naval Surface Warfare Center, are working with EOC researchers to create ultrahigh RF transistors, early prototypes of which have already been created in graphene by EOC materials scientist Joshua Robinson. The researcher's goal is to produce graphene transistors that are 100 times faster than silicon transistors.

Another group at EOC, researchers, Joshua Robinson, Mark Fanton, Brian Weiland, Kathleen Trumbull and Michael LaBella, are already at work on perfecting a non-sublimation technique for producing graphene wafers 200mm (8-inch) in diameter, which is the standard size used by most silicon fabrication equipment today.

- R. Colin Johnson
EE Times

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