Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Dealing with formal verification constraints

Posted: 19 Feb 2010 ?? ?Print Version ?Bookmark and Share

Keywords:formal verification? verification constraints? verification design?

The relentless increase in the number of transistors integrated on a single chip continues to take its toll on verification teams. Market pressures squeeze product development times, leaving little room for error. Simulation, with its established methodologies, continues to be the verification engineer's workhorse but is no longer the only choice. Simulation relies on test benches to generate stimulus that in turn finds bugs, but the absence of a bug in simulation is not evidence of design correctness. It simply means that the stimulus needed to expose the bug has not been applied or correctness checks are missing. Unfortunately, bugs may be still lurking in the design.

Desiring additional measures of design confidence, verification teams are increasingly turning to other verification technologies to augment simulation. Formal model checkers have become a good choice for block-level functional verification because they deliver mathematical proofs of correctness without requiring test bench development. However, there is no free lunch here. For formal tools to operate, they require two additional inputs: properties that specify the design's intended behavior; and constraints that specify legal input values for the design.

Properly constraining the design's inputs is the key to getting the most out of formal verification. Both over and under-constraining a design can lead to inaccurate results.

View the PDF document for more information.

Article Comments - Dealing with formal verification con...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top