EUV delay forces tool makers to check other options

Litho-Freeze-Litho-Etch—This "involves freezing one photoresist pattern, thereby eliminating one etch step, but still involves two critical litho steps that need to be correctly situated (over-laid) with respect to one another and uses only one etch step," according to Barclays Capital. "However, a major shortcoming of LFLE is that such a resist freezing method is only now being developed by JSR Ltd."

Spacer or self-aligned double-patterning (SADP)"The technology of choice for NAND," said Nikon's Ushida. "We do not need perfect alignment."

"With only one critical litho step, the method solves overlay as no alignment adjustment is necessary. All in all, it is more process flow intensive (using etch, CVD etc.) compared to litho intensive LELE and LFLE technology. Therefore, on the surface, SADP is more expensive for a new, green-field fab to implement," said Barclays Capital.

Source-mask optimization
"Source-mask optimization is limited," said Nikon's Ushida.

"As chip designs shrink, more and more source-mask tuning is required to maintain a workable process window, resulting in the need of many complex pupil shapes," according to ASML. "Faster, more flexible source tuning is essential for customers making full use of source and mask optimization (SMO).

Intel uses something called a pixelated mask. In another approach, ASML took SPIE to announce its new FlexRay programmable illumination system. Its FlexRay freeform illuminator claims to make it easier and faster to create and implement those custom shapes in volume manufacturing.

Dual-tone development
"Another promising contender is dual-tone development (DTD), in which a conventional exposure is followed by two development steps," according to a recent paper by Paul Zimmerman of Sematech.

"In positive-tone development, all material that has been exposed to some threshold dose is removed, while in negative-tone development, all material that has a threshold lower than a specific dose is removed. DTD may be a path to lowering cost of ownership. However, many materials issues must still be overcome. Additionally, line edge roughness (LER) is an issue in the development process, and the combination of two development steps may result in unacceptable LER," Zimmerman said.

Double-exposure
"This approach would have the lowest cost of ownership of all technologies and would eliminate the overlay concerns as the wafer does not leave the exposure tools between the two exposures," Zimmerman said in the paper. "However, this approach has several clear drawbacks. First, the necessary materials do not yet exist. Second, even if these materials are developed, their integration into a working resist system in a timeframe useful for integration into 22nm processing will be challenging. Since this process still uses diffusion, LER may limit the utility of this approach beyond the 22nm node."

- Mark LaPedus
EE Times

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