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TSMC takes on 40nm yields, high-k, litho issues

Posted: 01 Mar 2010 ?? ?Print Version ?Bookmark and Share

Keywords:TSMC 45nm issue? lithography? high-k metal gate? EUV?

At the TSMC Japan Executive Forum in Yokohama, Shang-Yi Chiang, senior VP of R&D at Taiwan Semiconductor Manufacturing Co. Ltd (TSMC), addressed several issues about the silicon foundry giant.

Chiang discussed TSMC's 40nm capacity, yield issues, high-k and lithography. EE Times obtained a transcript of the presentation. Here are some of the issues discussed:

40nm capacity
As previously reported, Nvidia Corp. and others are struggling to get their 40nm wafers from TSMC. "There are four major messages I'd like to deliver in this presentation. Number one is 40nm technology happened to be a very high demand in the early stage, so we saw the customer demand ramp up so quick, more than what we had seen before for 40nm, and we are working very hard to make up the volume," Chiang said.

He added, "At this stage we only have fab 12 ready to tape production of 40nm and we are able to do about 80,000 wafers per quarter at the moment. These are 12-inch wafers. And this will be doubled by the end of this year, to 160,000 12-inch wafers for 40nm capacity by the end of this year, and partly from fab 12 and partly from fab 14."

40nm yield challenge
TSMC also addressed the issues on its struggle with 40nm. "You all heard about TSMC's challenge during the early part of last year. I report to you we are glad all this problems was behind us. We resolve this yield problem in the second half of last year. So we're glad the yield issue was over, and we are building the capacity very aggressively to fulfill the very high demand from our customers."

Chiang added, "Moving to 45- and 40nm is a lot more challenging. This is the first time we began to use 193 nanometer shrink immersion. That means the photo resist during exposure will be merged in water and is a very high potential defect. For this a very big challenge, we began to develop the third generation. We began to use the second generation low k material with a k value of 2.5 and at this k value the material become quite fragile so there is a lot of potential issues in the package side. So moving to 40nm that's why it's getting pretty challenging, pretty difficult to do."

28nm progress
Several months ago, TSMC rolled out its 28nm, which will have several options. According to Chiang, "The first node we're going to release for the 28nm will be we call the 28 LP. This is our poly gate and silicon oxide nitrate version. We will establish production at the end of June this year, about four months from now, and this is for the low-power application. Again, no high-k metal gate."

Going high-k and metal gate
At 28nm, TSMC is expected to have a high-k/metal-gate option. "The first high-k metal gate we call 28 HP for the high performance application will be introduce the end of September this year, and followed by three months later December will be the 28 HPL. This is the first high-k metal gate introduction for the low power application," Chiang said.


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