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Reducing power consumption with low-power CPLD designs

Posted: 16 Mar 2010 ?? ?Print Version ?Bookmark and Share

Keywords:CPLD designs? low power consumption? reduce power consumption?

Any engineer involved with portable or handheld products knows that minimizing power consumption is a requirement for today's designs. But only the veterans understand the subtle yet important details that can stretch a systems' battery life to the maximum. In this article, we focus on how those seasoned experts use ultralow-power CPLDs to wring out every last microwatt from the I/O subsystems of their embedded designs.

We begin by reviewing how CPLDs are commonly used to shrink power, board space and BOM costs in embedded designs. Next, we look at how to minimize a CPLD's power consumption in its standby mode, not only by carefully selecting the device itself but also by choosing an appropriate bus parking scheme. Our exploration of power conservation during active operation include techniques such as selective logic gating, smart I/O design and precision supply voltage management.

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