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CMOS ADC handles 127Gbit/s PM-QPSK scheme

Posted: 24 Mar 2010 ?? ?Print Version ?Bookmark and Share

Keywords:ADC? CMOS? DSP? receiver?

Opnext Inc. has developed a low-power quad CMOS ADC, designed for use in a 127Gbit/s Polarization Multiplexed Quadrature Phase Shift Keying (PM-QPSK) modulation scheme.

Opnext worked with Mobius Semiconductor Inc. on the ADC, which will be integrated with a DSP core and forward error correction into a single PM-QPSK receiver chip using a standard CMOS process. This eliminates numerous connections between the ADC, DSP and the FEC.

The design includes continuous digital background self-calibration and synchronization. As a result the receiver is immune to process, voltage and temperature variations, allowing reliable performance over a broad range of operating conditions. The ADC naturally aligned with CMOS scaling and is portable will use a BGA package enabling volume SMT manufacturing.

Opnext continues to employ selective vertical integration on components such as the ADC with the goal of delivering the lowest cost and highest performance 100Gbit/s OIF MSA-compliant solution to its OEM partners.

Mobius uses digital signal processing assisted mixed-signal calibration techniques to develop a family of multi-gigasample data converters making possible integrated transceivers with significantly reduced cost, power and form factor. Mobius calibration technology is over different foundries and processes. Mobius is also developing low jitter ADPLLs, high-speed Serdes and DACs.

- Peter Clarke
EE Times

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