Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Memory/Storage

Configuring the SPEAr3xx multiport memory controller (MPMC) for external DDR SDRAM

Posted: 25 Mar 2010 ?? ?Print Version ?Bookmark and Share

Keywords:memory controller? external DDR SDRAM? DDR2 memory?

The SPEAr3xx embedded MPU family (SPEAr300, SPEAr310 and SPEAr320) features a multi-port memory controller for interfacing with external DDR or DDR2 memory devices.

In the SPEAr3xx embedded MPU, different memory controllers provide interfaces between the system elements/blocks and external memory.

The MPMC multi-port memory controller is used for interfacing DDR (double data rate) synchronous dynamic RAM (SDRAM). It is also responsible for reliable read-write operations to the memory. In a powerful system like SPEAr3xx, there are several system elements which may need to communicate with external DDR memory at any time to increase system efficiency. This is possible because the memory provides data at very high speed and system elements need time to process that data, so this time can be utilized by other system elements to transfer data to/from the memory. For example, during the time that the CPU processes some data or instructions, another master interface (CPU or DMA) can read or write to the memory. This can be handled by the MPMC's multi-port capability.

This application note describes how to configure the MPMC to use different types of DDR and DDR2 memories and tune the parameters in accordance with JEDEC requirements and the flexibility available in the application.

View the PDF document for more information.

Click here to view related datasheets.

Article Comments - Configuring the SPEAr3xx multiport m...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top