Quest for the right road to lithography

Once they're up to spec and available, the new scanners from ASML and Nikon could allow chipmakers to extend optical lithography deep into sub-30nm territory. But "the extension of immersion to 22 nm and below is likely to add to the cost and complexity, potentially making immersion at advanced nodes uneconomical," said Richard of Piper Jaffray.

The industry hopes NGL will then be ready to step in.

ASML and Nikon are also developing EUV scanners.

EUV push
EUV constitutes a major departure from today's tools. It uses a 13.5nm wavelength, and the processing steps take place in a vacuum chamber. The optical elements are basically defect-free mirrors that reflect light by means of interlayer interference.

Samsung is determined to insert EUV by 2012. It reportedly plans to start with DRAM production rather than NAND, which has become the industry driver for IC process scaling.

Click on image to enlarge.

"DRAM is more of a two-dimensional pattern, with three times more critical layers than NAND, and here is where we expect the industry to drive adoption of EUV," said Barclay's Muse. By contrast, NAND has a "one-dimensional" pattern, so for the 2xnm node NAND vendors should be able to get by with 193nm immersion and a double-patterning technology called spacer, he said. Spacer uses one critical lithography step, two critical etches and chemical vapor deposition to deposit a spacer film and hard mask.

Logic makers like Intel can postpone the shift to EUV because design rules are more relaxed for logic than for memory. "Intel is a half-pitch behind both NAND and DRAM," Muse noted.

Intel expects to use 193nm immersion down to 15nm, then pursue a mix-and-match strategy for 11nm that will pair a traditional scanner with EUV or maskless lithography, depending on which one is ready, said Yan Borodovsky, an Intel senior fellow and director of advanced lithography at the company's Technology and Manufacturing Group.

On the foundry side, Taiwan Semiconductor Manufacturing Co. Ltd has yet to make a decision among EUV, maskless and 193nm with double pattering.

With no clear chain of succession for lithography, chipmakers are even considering schemes that dispense with the technique. Novel approaches include stacking current devices in a 3-D configuration using through-silicon vias, as well as pursuing exotic structures and materials such as FinFETs and graphene transistors.

Like next-generation litho, however, for now these, too, are largely paper tigers.

- Mark LaPedus
EE Times

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