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IBM: Serious challenges await beyond 22nm

Posted: 12 Apr 2010 ?? ?Print Version ?Bookmark and Share

Keywords:design challenge? 22nm node? lithography? design flow?

IBM described a solution to "design rule explosion" at the 22nm node illustrated in an SRAM chip design.

IBM researcher Kevin Nowka warned of "design rule explosion" beyond the 22nm node during a presentation at the International Symposium on Physical Design (ISPD).

Senior manager of VLSI Systems at the IBM Austin Research Lab, Nowka described the physical design challenges beyond the 22nm node, emphasizing that sub-wavelength lithography has made silicon image fidelity a serious challenge.

"Simple technology abstractions that have worked for many generations like rectangular shapes, Boolean design rules, and constant parameters will not suffice to enable us to push designs to the ultimate levels of performance," Nowka said.

Solving "design rule explosion," according to Nowka, involves balancing area against image fidelity by considering the physical design needs at appropriate levels of abstraction, such as within cells. Nowka gave examples of how restricted design rules could reap a three-fold improvement in variability with a small area penalty.

Nowka envisions physical design rules beyond the 22nm node that are more technology-aware and which make use of pre-analysis and library optimization for improved density and robustness, he said.

'Thinking outside the chip'
Also at ISPD, Mentor Graphics Corp. proposed that hardware/software co-design be used for chips, their packages and their PCBs. A Mentor executive offered an example in which a 26 percent cost savings was realized by performing such a co-optimization of all three systems simultaneously.


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