Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Manufacturing/Packaging
?
?
Manufacturing/Packaging??

TSMC CEO calls for industry collaboration

Posted: 16 Apr 2010 ?? ?Print Version ?Bookmark and Share

Keywords:IC consolidation? Moore's Law? foundry?

While the near-term business outlook for semiconductors strong, the industry faces several challenges, according to Morris Chang, chairman and chief executive of Taiwan Semiconductor Manufacturing Co. Ltd.

During a keynote at TSMC's technology conference here, Chang said that Moore's Law is slowing and chip-production costs continue to soar. As a result, he said that there must be more collaboration than ever before between chipmakers and foundries, namely TSMC.

"We need to collaborate even before the design starts," he told the audience at the event. "I believe we can be far more collaborative."

As part of the equation, he also said that TSMC is committed to be "the technology leader." But in technology, TSMC is under pressure from some new and older foundry competitors, such as GlobalFoundries, Samsung and United Microelectronics Corp.

Fortunately, most foundries are seeing renewed demand following the nasty downturn. "Business is very good now," Chang said. "The near-term outlook is healthy. The mid-term outlook is moderate."

The IC market is expected to hit $276 billion in 2010, up 22 percent over 2009, according to Chang. In 2011, the IC market is expected to grow 7 percent, he said.

Going forward, however, there are some business challenges. "The semiconductor content in electronics is rising very slowly," he said, adding that the average selling prices for ICs continue to decline.

Over time, the industry will slow. From 2011-2014, the IC industry will see only a 4.2 percent average growth rate, he said.

On the technology front, there are also challenges. "Moore's Law is slowing down," he said. "R&D costs are escalating."

Top challenges
Here are the three major challenges outlined by Chang:

1. Scaling is becoming harder. "We have almost exhausted the optical lithography domain. We will be shifting to the non-optical lithography domain very quickly. (This in turn) means higher costs," Chang said.

2. Leakage has become a bigger problem. Interconnect complexity continues to be problematic.

3. Fab costs. Fewer and fewer chipmakers can build fabs. It's unclear how many chipmakers will build fabs for devices at 14- and 10nm. "If anyone will be there, TSMC will be there," he said. "We intend to remain the leader."

Seeking to take the technology lead in the silicon foundry business, TSMC is putting a new spin on its strategy: After the 28nm node, it plans to

skip the 22nm "full node" and will move directly to the 20nm "half node.

At its technology conference here, the world's largest silicon foundry also provided details about its 20nm CMOS process, which will be the company's main technology platform after the 28nm node. TSMC will also not offer an 18nm process.

- Mark LaPedus
EE Times





Article Comments - TSMC CEO calls for industry collabor...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top