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Multicore SoCs invade embedded arena

Posted: 20 Apr 2010 ?? ?Print Version ?Bookmark and Share

Keywords:multicore SoC? processor? OS? embedded market?

Predicting trends is difficult in most connected industry experts, but one trend that's easy to spot is the widespread acceptance of multicore SoC, which is happening for a number of reasons.

First, it's been years since the workstation first adopted the multicore processor architecture to solve such issues as increasing performance and power concerns. While the adoption rate in workstations is now saturated and is fully supported by General Purpose OS (GPOS), the embedded world is just now looking at ways to adopt multicore architecture.

Second, several SoC vendors have been providing multicore solutions including Cavium, Freescale, MIPS and ARM; but up until now, these solutions have been limited to networking and used for performance enhancements rather than for low power.

The rest of the embedded industry has had limited hardware options available as low-power design is a driving factor. While the ARM 11 MPCore was ahead of its time, the Cortex-A9 MPCore design is ready for primetime and is gaining acceptance in the embedded marketplace.

As a result, SoC vendors have adopted the Cortex-A9 MPCore hardware as a basis for their next-generation designs. Over a year ago, Texas Instruments pre-announced their next-generation OMAP designs in the OMAP 4 with a dual-core Cortex-A9 MPCore, scheduled for production in 2H 10. STMicroelectronics has pre-announced their next-generation consumer devices, which will be based on the Cortex A9 MPCore.

There has also been a shift in consumer electronics to adopt multicore hardware as demand for more processing power and complex user interfaces continue to increase.

So now it's time for the software to step upno more sitting on the sidelines. It's time to adapt and embrace the multicore hardware options available.

SMP, AMP development
One key concept when addressing multicore is to look at how the hardware is designed. This falls into two categories: Asymmetric Multi Processor (AMP) and Symmetric Multi Processor (SMP).

From the hardware perspective, AMP typically means the cores are architecturally different from one another. Each core can run different instruction sets with a corresponding operating system, or even no operating system at all.

In AMP, an OS typically executes on a single core with some method (likely proprietary) to communicate between cores. It runs all the devices at its disposal with minimal sharing of resources.

In contrast SMP capable hardware consists of CPU cores that are identical. These cores all service the same events, have the same instruction set, see the same memory, and share the same devices, interrupts, and share a cache coherency unit. This allows for load balancing between cores.

An SMP capable OS can utilize all the cores at its disposal by scheduling threads and servicing devices and interrupts on any core in the SMP domain.

So is it possible to take advantage of AMP on SMP hardware? The answer is yes, but just because the hardware is capable of true SMP, doesn't mean the best solution is to run all cores in SMP mode. There are optimizations where the system can and should be divided between several operating systems. This is AMP on SMP hardware.

A hybrid approach (see figure below) may be ideal where the SMP hardware is divided between OS domains where each domain functions across multiple cores. For example, take a four-core SMP capable SoC.


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